1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, in particular an electrostatic discharge (ESD) protection circuit for preventing damage to an internal circuit element due to overvoltage from static electricity. The present application is based on Japanese Patent Application No. 178770/2000, which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional electrostatic protection circuit. FIG. 2 is a circuit diagram showing another conventional electrostatic protection circuit.
As shown in FIG. 1, the conventional electrostatic protection circuit comprises by N-channel MOSFET (hereinafter called nMOSFET) Qn5 which is inserted between an input terminal IN connected to an internal circuit element to be protected and the ground GND. The drain (D) of nMOSFET Qn5 is connected to the input terminal IN. The gate (G), the source (S) and the substrate (B) are grounded.
When a negative voltage is applied to the input terminal IN of the conventional electrostatic protection circuit, current flows from the ground GND to the input terminal IN via a PN junction between the substrate (B) and the drain (D) of nMOSFET Qn5. Therefore, the negative overvoltage applied to the input terminal IN is clamped.
In the meantime, when a positive overvoltage is applied to the input terminal IN, current flow from the input terminal IN to the ground GND via the parasitic bipolar transistor of nMOSFET Qn5. Therefore, the positive overvoltage applied to the input terminal IN is clamped. This is a phenomenon caused by the conduction of parasitic bipolar transistor composed of the source (S), the substrate (B) and the drain (D) of nMOSFET Qn5 due to the voltage drop that occurs because of substrate resistance when a substrate current originated in impact ionization at the end of the drain flows. The phenomenon shows current (I)-voltage (Vin) characteristics having negative resistance called snapback as shown in FIG. 3.
Voltage Vt1 where a high-resistance region in charged to a low-resistance region due to the conduction of a parasitic bipolar transistor is called the trigger voltage. Normally, trigger voltage Vt1 is set to be lower than the breakdown voltage of a MOSFET of an internal circuit element (i.e., the breakdown voltage of a gate oxide film).
An electrostatic protection circuit shown in FIG. 2 includes P-channel MOSFET (hereinafter called pMOSFET) Qp5 in addition to the electrostatic protection circuit shown in FIG. 1. The drain (D) of pMOSFET Qp5 is connected to an input terminal IN. The gate (G), the source (S) and the substrate (B) of pMOSFET Qp5 are connected to the power supply Vdd.
The electrostatic protection circuit shown in FIG. 2 is operated like the electrostatic protection circuit shown in FIG. 1 in the case that the power supply Vdd is open. When the ground GND is open and a positive voltage exceeding the power supply Vdd is applied to the input terminal IN, current flows from the input terminal IN to the power supply Vdd via a PN junction between the drain (D) and the substrate (B) of pMOSFET Qp5. Therefore, positive overvoltage applied to the input terminal IN is clamped.
On the other hand, when a negative overvoltage is applied to the input terminal IN, a parasitic bipolar transistor of pMOSFET Qp5 conducts, and a current flows from the power supply Vdd to the input terminal IN via the drain (D), the substrate (B) and the source (S) of pMOSFET Qn5. Therefore, the negative overvoltage applied to the input terminal IN is clamped.
Thus, the breakdown of the internal circuit element of a semiconductor integrated circuit is prevented from overvoltage applied to the input terminal IN as described above.
Due to the scaling of semiconductor integrated circuits, the breakdown voltage has become relatively low. For example, for a MOSFET with a gate length of 0.35 xcexcm, the thickness of a gate oxide film is 7 to 8 nm. For a MOSFET with a gate length of 0.25 xcexcm, the thickness of the gate oxide film is 5 to 6 nm. For a MOSFET with a gate length of 0.18 xcexcm, the gate oxide film is 3.5 to 4 nm. The breakdown voltage of the gate oxide film is approximately 15 MV/cm. Thus, for a MOSFET with a gate length of 0.35 xcexcm, the breakdown voltage is approximately 10 to 12 V. For a MOSFET with a gate length of 0.25 xcexcm, the breakdown voltage is approximately 7 to 9 V.
MOSFET with a gate length of 0.18 xcexcm, the breakdown voltage is approximately 5 to 6 V.
Since overvoltage due to static electricity is transient, the gate oxide film may not be broken at once even if a voltage exceeding the breakdown voltage described above is applied. However, in that case, reliability may be deteriorated due to the variation of transistor characteristics.
As described above, the electrostatic protection circuits shown in FIG. 1 and FIG. 2 control the overvoltage by utilizing the MOSFET snapback current-voltage characteristics shown in FIG. 3. This is based on the fact that a resistance value of the parasitic bipolar transistor is smaller than a normal on-state resistance value of MOSFET.
As the breakdown voltage of the internal circuit element becomes lower, trigger voltage Vt1 must be a smaller value. However, as it is difficult to set trigger voltage Vt1 to desired voltage only by varying various parameters of a MOSFET, the trigger voltage Vt1 cannot be set to sufficiently low voltage. Therefore, it is difficult to protect an internal circuit element.
The present invention solves the problems that the electrostatic circuit of the related art described above has. One of the objects is to provide an electrostatic protection circuit wherein trigger voltage for causing the snapback operation of MOSFET is reduced and a circuit element having a low breakdown voltage can be protected.
In one aspect of the present invention, an electrostatic protection circuit is provided to prevent the breakdown of an internal circuit element of a semiconductor integrated circuit from overvoltage by static electricity. The electrostatic protection circuit comprises a protection nMOSFET in which the drain is connected to an input/output terminal and the source and the substrate are grounded. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a resistor connected between the gate of the protection nMOSFET and ground. The resistor is characterized in that the number of diodes composing the diode array and a value of the resistor are set so that the protection nMOSFET is kept off when voltage applied to the input-output terminal is between ground potential and supply voltage. The resistor is further characterized in that the nMOSFET is turned on and a parasitic bipolar transistor conducts when the voltage applied to the input/output terminal exceeds the supply voltage.
A second aspect of the present invention provides an electrostatic protection circuit comprising a protection nMOSFET, in which the drain is connected to an input/output terminal, and the source and the gate are grounded. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the substrate of the protection nMOSFET and the input-output terminal. The electrostatic protection circuit further comprises a resistor connected between the substrate of the protection nMOSFET and ground. The resistor is characterized in that the number of diodes composing the diode array and a value of the resistor are set so that the protection nMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The resistor is further characterized such that current flows from the substrate of the protection nMOSFET to the source and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal exceeds the supply voltage.
It is desirable that the resistor is a nMOSFET set to an off state.
A third aspect of the present invention provides an electrostatic protection circuit comprising a protection nMOSFET in which the drain is connected to an input/output terminal, and the source and the substrate are grounded. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a first resistor connected in parallel with the diode array between the gate of the protection nMOSFET and the input-output terminal. The electrostatic protection circuit further comprises a second resistor connected between the gate of the protection nMOSFET and the ground. Each value of the first resistor and the second resistor is set so that the protection nMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The number of diodes composing the diode array and a value of the second resistor are set so that the protection nMOSFET is turned on and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal exceeds the supply voltage.
A fourth aspect of the present invention provides an electrostatic protection circuit comprising a protection nMOSFET in which the drain is connected to an input/output terminal, and the source and the gate are grounded. The electrostatic protection circuit also comprises a diode array, composed of at least one diode, connected in series in a forward direction between the substrate of the protection nMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a first resistor connected in parallel with the diode array between the substrate of the protection nMOSFET and the input/output terminal and a second resistor connected between the substrate of the protection nMOSFET and the ground. Each value of the first resistor and the second resistor is set so that the protection nMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The number of diodes composing the diode array and a value of the second resistor are set so that current flows from the substrate of the protection nMOSFET to the source and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal exceeds the supply voltage.
It is desirable that the first resistor and the second resistor are nMOSFETs set to an off state.
A fifth aspect of the present invention provides an electrostatic protection circuit comprising a protection pMOSFET in which the drain is connected to an input/output terminal and the source and the substrate are connected to a power supply. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the gate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a resistor connected between the gate of the protection pMOSFET and the power supply. The resistor is characterized in that the number of diodes composing the diode array and a value of the resistor are set so that the protection pMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The resistor is further characterized in that the protection pMOSFET is turned on and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal is less than the ground potential.
A sixth aspect of the present invention provides an electrostatic protection circuit comprising a protection pMOSFET in which the drain is connected to an input/output terminal, and the source and the gate are connected to a power supply. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the substrate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a resistor connected between the substrate of the protection pMOSFET and the power supply. The resistor is characterized in that the number of diodes composing the diode array and a value of the resistor are set so that the protection pMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The resistor is further characterized in that current flows from the source of the protection pMOSFET to the substrate and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal is less than the ground potential.
It is desirable that the resistor is a pMOSFET set to an off state.
A seventh aspect of the present invention provides an electrostatic protection circuit comprising a protection pMOSFET in which the drain is connected to an input/output terminal, and the source and the substrate are connected to a power supply. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the gate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a first resistor connected in parallel with the diode array between the gate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a second resistor connected between the gate of the protection pMOSFET and power supply. The value of the first resistor and the second resistor is set so that the protection pMOSFET is kept off when voltage applied to the input-output terminal is between ground potential and supply voltage. The number of diodes composing the diode array and the value of the second resistor are set so that the protection pMOSFET,T is turned on and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal is less than the ground potential.
An eighth aspect of the present invention provides an electrostatic protection circuit comprising protection pMOSFET in which the drain is connected to an input/output terminal, and the source and the gate are connected to a power supply. The electrostatic protection circuit further comprises a diode array, composed of at least one diode, connected in series in a forward direction between the substrate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a first resistor connected in parallel with the diode array between the substrate of the protection pMOSFET and the input/output terminal. The electrostatic protection circuit further comprises a second resistor connected between the substrate of the protection pMOSFET and power supply. The value of the first resistor and the second resistor are set so that the protection pMOSFET is kept off when voltage applied to the input/output terminal is between ground potential and supply voltage. The number of diodes composing the diode array and the value of the second resistor are set so that current flows from the source of the protection pMOSFET to the substrate and a parasitic bipolar transistor conducts when voltage applied to the input/output terminal is less than the ground potential.
It is desirable that the first resistor and the second resistor are pMOSFETs set to an off state.
Furthermore, the nMOSFET, the diode array and the resistor connected to the protection nMOSFET and the pMOSFET, the diode array and the resistor connected to the protection pMOSFET can be combined.
In the electrostatic protection circuit described above, when the voltage applied to the input/output terminal exceeds supply voltage or is less than ground potential, the substrate current of the protection nMOSFET or the protection pMOSFET increases and trigger voltage for snapback can be reduced.